GD32VF103 User Manual
207
This register can be accessed by half-word(16-bit) or word(32-bit) access
Must be kept at reset value
Free watchdog timer counter reload value update
During a write operation to FWDGT_RLD register, this bit is set and the value read
from FWDGT_RLD register is invalid. This bit is reset by hardware after the update
operation of FWDGT_RLD register.
Free watchdog timer prescaler value update
During a write operation to FWDGT_PSC register, this bit is set and the value read
from FWDGT_PSC register is invalid. This bit is reset by hardware after the update
operation of FWDGT_PSC register.
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