GigaDevice Semiconductor GD32VF103 - Page 502

GD32VF103 User Manual
502
r
Bits
Fields
Descriptions
31:8
Reserved
Must be kept at reset value
7:0
HACHINT[7:0]
Host all channel interrupts
Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7.
Host all channels interrupt enable register (USBFS_HACHINTEN)
Address offset: 0x0418
Reset value: 0x0000 0000
This register can be used by software to enable or disable a channel’s interrupt. Only the
channel whose corresponding bit in this register is set is able to cause the channel interrupt
flag HCIF in USBFS_GINTF register.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CINTEN[7:0]
rw
Bits
Fields
Descriptions
31:8
Reserved
Must be kept at reset value
7:0
CINTEN[7:0]
Channel interrupt enable
0: Disable channel-n interrupt
1: Enable channel-n interrupt
Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7.
Host port control and status register (USBFS_HPCS)
Address offset: 0x0440
Reset value: 0x0000 0000
This register controls the port’s behavior and also has some flags which report the status of
the port. The HPIF flag in USBFS_GINTF register will be triggered if one of these flags in this