GigaDevice Semiconductor GD32VF103 - Page 86

GD32VF103 User Manual
86
0: Disabled I2C1 clock
1: Enabled I2C1 clock
21
I2C0EN
I2C0 clock enable
This bit is set and reset by software.
0: Disabled I2C0 clock
1: Enabled I2C0 clock
20
UART4EN
UART4 clock enable
This bit is set and reset by software.
0: Disabled UART4 clock
1: Enabled UART4 clock
19
UART3EN
UART3 clock enable
This bit is set and reset by software.
0: Disabled UART3 clock
1: Enabled UART3 clock
18
USART2EN
USART2 clock enable
This bit is set and reset by software.
0: Disabled USART2 clock
1: Enabled USART2 clock
17
USART1EN
USART1 clock enable
This bit is set and reset by software.
0: Disabled USART1 clock
1: Enabled USART1 clock
16
Reserved
Must be kept at reset value
15
SPI2EN
SPI2 clock enable
This bit is set and reset by software.
0: Disabled SPI2 clock
1: Enabled SPI2 clock
14
SPI1EN
SPI1 clock enable
This bit is set and reset by software.
0: Disabled SPI1 clock
1: Enabled SPI1 clock
13:12
Reserved
Must be kept at reset value
11
WWDGTEN
WWDGT clock enable
This bit is set and reset by software.
0: Disabled WWDGT clock
1: Enabled WWDGT clock
10:6
Reserved
Must be kept at reset value
5
TIMER6EN
TIMER6 clock enable