10 Datasheet
10.1.55CIR33—Chipset Initialization Register 33..................................................396
10.1.56CIR34—Chipset Initialization Register 34..................................................396
10.1.57CIR12—Chipset Initialization Register 12..................................................397
10.1.58CIR14—Chipset Initialization Register 14..................................................397
10.1.59CIR15—Chipset Initialization Register 15..................................................397
10.1.60CIR13—Chipset Initialization Register 13..................................................397
10.1.61CIR16—Chipset Initialization Register 16..................................................397
10.1.62CIR18—Chipset Initialization Register 18..................................................397
10.1.63CIR17—Chipset Initialization Register 17..................................................398
10.1.64CIR23—Chipset Initialization Register 23..................................................398
10.1.65CIR19—Chipset Initialization Register 19..................................................398
10.1.66PMSYNC Configuration...........................................................................398
10.1.67CIR20—Chipset Initialization Register 20..................................................399
10.1.68CIR21—Chipset Initialization Register 21..................................................399
10.1.69CIR22—Chipset Initialization Register 22..................................................399
10.1.70RC—RTC Configuration Register..............................................................400
10.1.71HPTC—High Precision Timer Configuration Register ...................................400
10.1.72GCS—General Control and Status Register ...............................................401
10.1.73BUC—Backed Up Control Register ...........................................................403
10.1.74FD—Function Disable Register ................................................................403
10.1.75CG—Clock Gating..................................................................................406
10.1.76FDSW—Function Disable SUS Well ..........................................................407
10.1.77DISPBDF—Display Bus, Device and Function Initialization...........................408
10.1.78FD2—Function Disable 2 ........................................................................408
10.1.79MISCCTL—Miscellaneous Control Register ................................................409
10.1.80USBOCM1—Overcurrent MAP Register 1...................................................410
10.1.81USBOCM2—Overcurrent MAP Register 2...................................................411
10.1.82RMHWKCTL—Rate Matching Hub Wake Control Register.............................412
10.1.83CIR24—Chipset Initialization Register 24..................................................413
10.1.84CIR25—Chipset Initialization Register 25..................................................413
10.1.85CIR26—Chipset Initialization Register 26..................................................413
10.1.86CIR27—Chipset Initialization Register 27..................................................413
10.1.87CIR28—Chipset Initialization Register 28..................................................414
10.1.88CIR29—Chipset Initialization Register 29..................................................414
11 PCI-to-PCI Bridge Registers (D30:F0)....................................................................415
11.1 PCI Configuration Registers (D30:F0).................................................................415
11.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0).............................416
11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0).............................416
11.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0) .............................................416
11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)..........................................417
11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................419
11.1.6 CC—Class Code Register (PCI-PCI—D30:F0).............................................419
11.1.7 PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)................................................................................420
11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) .................................420
11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ......................................420
11.1.10SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0)................................................................................421
11.1.11IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0)................................................................................421
11.1.12SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................422
11.1.13MEMBASE_LIMIT—Memory Base and Limit Register
(PCI-PCI—D30:F0)................................................................................423
11.1.14PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
and Limit Register (PCI-PCI—D30:F0) .....................................................423
11.1.15PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0) ...................................................................424
11.1.16PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0) ...................................................................424
11.1.17CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) ..........................424
11.1.18INTR—Interrupt Information Register (PCI-PCI—D30:F0)...........................424
11.1.19BCTRL—Bridge Control Register (PCI-PCI—D30:F0)...................................425
11.1.20SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0)................................................................................427
11.1.21DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0)................................................................................427
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