Datasheet 135
Functional Description
5.5.1.2 Rotating Priority
Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the
last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).
Channels 0–3 rotate as a group of 4. They are always placed between Channel 5 and
Channel 7 in the priority list.
Channel 5–7 rotate as part of a group of 4. That is, Channels (5–7) form the first three
positions in the rotation, while Channel Group (0–3) comprises the fourth position in
the arbitration.
5.5.2 Address Compatibility Mode
When the DMA is operating, the addresses do not increment or decrement through the
High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments,
the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h
and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is
operating in 16-bit mode, the addresses still do not increment or decrement through
the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a
24-bit address is 01FFFEh and increments, the next address is 000000h, not
0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address
is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register
implementation used in the PC-AT. This mode is set after CPURST is valid.
5.5.3 Summary of DMA Transfer Sizes
Table 5-12 lists each of the DMA device transfer sizes. The column labeled “Current
Byte/Word Count Register” indicates that the register contents represents either the
number of bytes to transfer or the number of 16-bit words to transfer. The column
labeled “Current Address Increment/Decrement” indicates the number added to or
taken from the Current Address register after each DMA transfer cycle. The DMA
Channel Mode Register determines if the Current Address Register will be incremented
or decremented.
5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words
The PCH maintains compatibility with the implementation of the DMA in the PC AT that
used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device
count-by-words.
Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.
When programming the Current Address Register (when the DMA channel is in this
mode), the Current Address must be programmed to an even address with the address
value shifted right by one bit.
Table 5-12. DMA Transfer Size
DMA Device Date Size And Word Count
Current Byte/Word
Count Register
Current Address
Increment/
Decrement
8-Bit I/O, Count By Bytes Bytes 1
16-Bit I/O, Count By Words (Address
Shifted)
Words 1
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