Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Table of Contents

Datasheet 3
Contents
1Introduction............................................................................................................41
1.1 About This Manual.............................................................................................41
1.2 Overview .........................................................................................................44
1.2.1 Capability Overview................................................................................ 45
1.3 Intel
®
6 Series Chipset SKU Definition .................................................................51
2 Signal Description ...................................................................................................53
2.1 Direct Media Interface (DMI) to Host Controller.....................................................55
2.2 PCI Express* ....................................................................................................55
2.3 PCI Interface ....................................................................................................56
2.4 Serial ATA Interface...........................................................................................58
2.5 LPC Interface....................................................................................................61
2.6 Interrupt Interface ............................................................................................61
2.7 USB Interface...................................................................................................62
2.8 Power Management Interface.............................................................................. 63
2.9 Processor Interface............................................................................................67
2.10 SMBus Interface................................................................................................67
2.11 System Management Interface............................................................................68
2.12 Real Time Clock Interface...................................................................................68
2.13 Miscellaneous Signals ........................................................................................69
2.14 Intel
®
High Definition Audio Link.........................................................................70
2.15 Controller Link..................................................................................................71
2.16 Serial Peripheral Interface (SPI)..........................................................................71
2.17 Thermal Signals ................................................................................................71
2.18 Testability Signals .............................................................................................72
2.19 Clock Signals....................................................................................................72
2.20 LVDS Signals....................................................................................................74
2.21 Analog Display /VGA DAC Signals........................................................................75
2.22 Intel
®
Flexible Display Interface (Intel
®
FDI)........................................................76
2.23 Digital Display Signals........................................................................................77
2.24 General Purpose I/O Signals ...............................................................................80
2.25 Manageability Signals ........................................................................................84
2.26 Power and Ground Signals..................................................................................85
2.27 Pin Straps ........................................................................................................87
2.28 External RTC Circuitry........................................................................................91
3PCH Pin States.........................................................................................................93
3.1 Integrated Pull-Ups and Pull-Downs.....................................................................93
3.2 Output and I/O Signals Planes and States.............................................................95
3.3 Power Planes for Input Signals.......................................................................... 107
4 PCH and System Clocks ......................................................................................... 113
4.1 Platform Clocking Requirements........................................................................ 113
4.2 Functional Blocks ............................................................................................ 115
4.3 Clock Configuration Access Overview ................................................................. 116
4.4 Straps Related to Clock Configuration ................................................................ 116
5 Functional Description........................................................................................... 117
5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 117
5.1.1 PCI Legacy Mode.................................................................................. 117
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7)..................................... 118
5.2.1 Interrupt Generation............................................................................. 118
5.2.2 Power Management.............................................................................. 119
5.2.2.1 S3/S4/S5 Support................................................................... 119
5.2.2.2 Resuming from Suspended State .............................................. 119
5.2.2.3 Device Initiated PM_PME Message............................................. 119
5.2.2.4 SMI/SCI Generation................................................................ 120
5.2.3 SERR# Generation ............................................................................... 120
5.2.4 Hot-Plug ............................................................................................. 120
5.2.4.1 Presence Detection ................................................................. 121
5.2.4.2 Message Generation................................................................ 121
5.2.4.3 Attention Button Detection....................................................... 121