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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
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Functional Description
162 Datasheet
Table 5-25 shows the transitions rules among the various states. Note that transitions
among the various states may appear to temporarily transition through intermediate
states. For example, in going from S0 to S3, it may appear to pass through the G1/S1
states. These intermediate transitions and states are not listed in the table.
NOTES:
1. Some wake events can be preserved through power failure.
2. Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is
inactive in mobile configurations.
G2/S5
Soft Off (SOFF): System context is not maintained. All power is shut off except
for the logic required to restart. A full boot is required when waking.
G2/Deep S5
Soft Off (SOFF): System context is not maintained. All power is shut off except
for minimal logic that allows exiting Deep S5. A full boot is required when
waking.
G3
Mechanical OFF (MOFF): System context not maintained. All power is shut off
except for the RTC. No “Wake” events are possible. This state occurs if the user
removes the main system batteries in a mobile system, turns off a mechanical
switch, or if the system power supply is at a level that is insufficient to power the
“waking” logic. When system power returns, transition will depend on the state
just prior to the entry to G3 and the AFTERG3 bit in the GEN_PMCON3 register
(D31:F0, offset A4). Refer to Table 5-31 for more details.
Table 5-24. General Power States for Systems Using the PCH (Sheet 2 of 2)
State/
Substates
Legacy Name / Description
Table 5-25. State Transition Rules for the PCH
Present
State
Transition Trigger Next State
G0/S0/C0
•DMI Msg
•SLP_EN bit set
Power Button Override
Mechanical Off/Power Failure
•G0/S0/Cx
•G1/Sx or G2/S5 state
•G2/S5
•G3
G0/S0/Cx
•DMI Msg
Power Button Override
Mechanical Off/Power Failure
•G0/S0/C0
•S5
•G3
G1/S1,
G1/S3, or
G1/S4
Any Enabled Wake Event
Power Button Override
Mechanical Off/Power Failure
G0/S0/C0 (See Note 2)
•G2/S5
•G3
G2/S5
Any Enabled Wake Event
Mechanical Off/Power Failure
G0/S0/C0 (See Note 2)
•G3
G3 Power Returns
Optional to go to S0/C0 (reboot) or G2/S5
(stay off until power button pressed or
other wake event). (See Notes 1 and 2)

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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General IconGeneral
BrandIntel
Model6 SERIES CHIPSET - DATASHEET 01-2011
CategoryController
LanguageEnglish

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