Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - DMA Registers

LPC Interface Bridge Registers (D31:F0)
474 Datasheet
13.2 DMA I/O Registers
Table 13-2. DMA Registers (Sheet 1 of 2)
Port Alias Register Name Default Type
00h 10h
Channel 0 DMA Base & Current Address
Undefined R/W
01h 11h
Channel 0 DMA Base & Current Count
Undefined R/W
02h 12h
Channel 1 DMA Base & Current Address
Undefined R/W
03h 13h
Channel 1 DMA Base & Current Count
Undefined R/W
04h 14h
Channel 2 DMA Base & Current Address
Undefined R/W
05h 15h
Channel 2 DMA Base & Current Count
Undefined R/W
06h 16h
Channel 3 DMA Base & Current Address
Undefined R/W
07h 17h
Channel 3 DMA Base & Current Count
Undefined R/W
08h 18h
Channel 0–3 DMA Command
Undefined WO
Channel 0–3 DMA Status
Undefined RO
0Ah 1Ah
Channel 0–3 DMA Write Single Mask
000001XXb WO
0Bh 1Bh
Channel 0–3 DMA Channel Mode
000000XXb WO
0Ch 1Ch
Channel 0–3 DMA Clear Byte Pointer
Undefined WO
0Dh 1Dh
Channel 0–3 DMA Master Clear
Undefined WO
0Eh 1Eh
Channel 0–3 DMA Clear Mask
Undefined WO
0Fh 1Fh
Channel 0–3 DMA Write All Mask
0Fh R/W
80h 90h
Reserved Page
Undefined R/W
81h 91h
Channel 2 DMA Memory Low Page
Undefined R/W
82h —
Channel 3 DMA Memory Low Page
Undefined R/W
83h 93h
Channel 1 DMA Memory Low Page
Undefined R/W
84h–86h 94h–96h
Reserved Pages
Undefined R/W
87h 97h
Channel 0 DMA Memory Low Page
Undefined R/W
88h 98h
Reserved Page
Undefined R/W
89h 99h
Channel 6 DMA Memory Low Page
Undefined R/W
8Ah 9Ah
Channel 7 DMA Memory Low Page
Undefined R/W
8Bh 9Bh
Channel 5 DMA Memory Low Page
Undefined R/W
8Ch–8Eh 9Ch–9Eh
Reserved Page
Undefined R/W
8Fh 9Fh
Refresh Low Page
Undefined R/W
C0h C1h
Channel 4 DMA Base & Current Address
Undefined R/W
C2h C3h
Channel 4 DMA Base & Current Count
Undefined R/W
C4h C5h
Channel 5 DMA Base & Current Address
Undefined R/W
C6h C7h
Channel 5 DMA Base & Current Count
Undefined R/W
C8h C9h
Channel 6 DMA Base & Current Address
Undefined R/W
CAh CBh
Channel 6 DMA Base & Current Count
Undefined R/W
CCh CDh
Channel 7 DMA Base & Current Address
Undefined R/W