Datasheet 129
Functional Description
5.3.6.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset completes. This bit can be
used to indicate to the software that the FLR reset completed.
Note: From the time the Initiate FLR bit is written to 1b, software must wait at least 100 ms
before accessing the function.
5.4 LPC Bridge (with System and Management
Functions) (D31:F0)
The LPC bridge function of the PCH resides in PCI Device 31:Function 0. In addition to
the LPC bridge function, D31:F0 contains other functional units including DMA,
Interrupt controllers, Timers, Power Management, System Management, GPIO, and
RTC. In this chapter, registers and functions associated with other functional units
(power management, GPIO, USB, etc.) are described in their respective sections.
Note: The LPC bridge cannot be configured as a subtractive decode agent.
5.4.1 LPC Interface
The PCH implements an LPC interface as described in the Low Pin Count Interface
Specification, Revision 1.1. The LPC interface to the PCH is shown in Figure 5-2. Note
that the PCH implements all of the signals that are shown as optional, but peripherals
are not required to do so.
Figure 5-2. LPC Interface Diagram
PCH
LPC Device
PCI Bus
PCI
CLK
PCI
RST#
PCI
SERIRQ
PCI
PME#
LAD [3:0]
LFRAME#
LPCPD#
(Optional)
SUS_STAT#
LDRQ[1:0]#
(Optional)
LSMI#
(Optional)
GPI
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