Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - A20 M# (Mask A20); A20 GATE; Processor Interface (D31:F0); Processor Interface Signals and VLW Messages

Functional Description
158 Datasheet
5.12 Processor Interface (D31:F0)
The PCH interfaces to the processor with following pin-based signals other than DMI:
• Standard Outputs to processor: PROCPWRGD, PMSYNCH, PECI
• Standard Input from processor: THRMTRIP#
Most PCH outputs to the processor use standard buffers. The PCH has separate
V_PROC_IO signals that are pulled up at the system level to the processor voltage, and
thus determines VOH for the outputs to the processor.
The following processor interface legacy pins were removed from the PCH:
• IGNNE#, STPCLK#, DPSLP#, are DPRSLPVR are no longer required on PCH based
systems.
• A20M#, SMI#, NMI, INIT#, INTR, FERR#: Functionality has been replaced by in-
band Virtual Legacy Wire (VLW) messages. See Section 5.12.3.
5.12.1 Processor Interface Signals and VLW Messages
This section describes each of the signals that interface between the PCH and the
processor(s). Note that the behavior of some signals may vary during processor reset,
as the signals are used for frequency strapping.
5.12.1.1 A20M# (Mask A20) / A20GATE
The A20M# VLW message is asserted when both of the following conditions are true:
• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0
• The A20GATE input signal is a 0
The A20GATE input signal is expected to be generated by the external microcontroller
(KBC).