Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - PIC Registers

Datasheet 485
LPC Interface Bridge Registers (D31:F0)
13.3.3 Counter Access Ports Register
I/O Address: Counter 0 – 40h,
Counter 1
– 41h, Attribute: R/W
Counter 2
– 42h
Default Value: All bits undefined Size: 8 bit
13.4 8259 Interrupt Controller (PIC) Registers
13.4.1 Interrupt Controller I/O MAP
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers
have multiple functions, depending upon the data written to them. Table 13-3 shows
the different register possibilities for each address.
Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers
section (Chapter 5.8).
Bit Description
7:0
Counter Port — R/W. Each counter port address is used to program the 16-bit Count
Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is
defined with the Interval Counter Control Register at port 43h. The counter port is also
used to read the current count from the Count Register, and return the status of the
counter programming following a Read Back Command.
Table 13-3. PIC Registers
Port Aliases Register Name
Default
Value
Type
20h
24h, 28h,
2Ch, 30h,
34h, 38h, 3Ch
Master PIC ICW1 Init. Cmd Word 1 Undefined WO
Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO
Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO
21h
25h, 29h,
2Dh, 31h,
35h, 39h,
3Dh
Master PIC ICW2 Init. Cmd Word 2 Undefined WO
Master PIC ICW3 Init. Cmd Word 3 Undefined WO
Master PIC ICW4 Init. Cmd Word 4 01h WO
Master PIC OCW1 Op Ctrl Word 1 00h R/W
A0h
A4h, A8h,
ACh, B0h,
B4h, B8h,
BCh
Slave PIC ICW1 Init. Cmd Word 1 Undefined WO
Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO
Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO
A1h
A5h, A9h,
ADh, B1h,
B5h, B9h,
BDh
Slave PIC ICW2 Init. Cmd Word 2 Undefined WO
Slave PIC ICW3 Init. Cmd Word 3 Undefined WO
Slave PIC ICW4 Init. Cmd Word 4 01h WO
Slave PIC OCW1 Op Ctrl Word 1 00h R/W
4D0h – Master PIC Edge/Level Triggered 00h R/W
4D1h – Slave PIC Edge/Level Triggered 00h R/W