Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Configuration Bits Reset by RTCRST# Assertion

Datasheet 157
Functional Description
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The
system is booted with the jumper in new position, then powered back down. The
jumper is replaced back to the normal position, then the system is rebooted again.
Warning: Do not implement a jumper on VccRTC to clear CMOS.
Table 5-21. Configuration Bits Reset by RTCRST# Assertion
Bit Name Register Location Bit(s)
Default
State
Alarm Interrupt
Enable (AIE)
Register B (General
Configuration) (RTC_REGB)
I/O space (RTC Index
+ 0Bh)
5X
Alarm Flag (AF)
Register C (Flag Register)
(RTC_REGC)
I/O space (RTC Index
+ 0Ch)
5X
SWSMI_RATE_SEL
General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 7:6 0
SLP_S4# Minimum
Assertion Width
General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 5:4 0
SLP_S4# Assertion
Stretch Enable
General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 3 0
RTC Power Status
(RTC_PWR_STS)
General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 2 0
Power Failure
(PWR_FLR)
General PM Configuration 3
Register (GEN_PMCON_3)
D31:F0:A4h 1 0
AFTERG3_EN
General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 0 0
Power Button
Override Status
(PRBTNOR_STS)
Power Management 1 Status
Register (PM1_STS)
PMBase + 00h 11 0
RTC Event Enable
(RTC_EN)
Power Management 1 Enable
Register (PM1_EN)
PMBase + 02h 10 0
Sleep Type
(SLP_TYP)
Power Management 1 Control
(PM1_CNT)
PMBase + 04h 12:10 0
PME_EN
General Purpose Event 0
Enables Register (GPE0_EN)
PMBase + 2Ch 11 0
BATLOW_EN
General Purpose Event 0
Enables Register (GPE0_EN)
PMBase + 2Ch 10 0
RI_EN
General Purpose Event 0
Enables Register (GPE0_EN)
PMBase + 2Ch 8 0
NEWCENTURY_ST
S
TCO1 Status Register
(TCO1_STS)
TCOBase + 04h 7 0
Intruder Detect
(INTRD_DET)
TCO2 Status Register
(TCO2_STS)
TCOBase + 06h 0 0
Top Swap (TS)
Backed Up Control Register
(BUC)
Chipset Config
Registers:Offset 3414h
0X