Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Registers to Control GPIO Address Map

Datasheet 541
LPC Interface Bridge Registers (D31:F0)
13.10 General Purpose I/O Registers
The control for the general purpose I/O signals is handled through a 128-byte I/O
space. The base offset for this space is selected by the GPIOBASE register.
Table 13-13. Registers to Control GPIO Address Map
GPIOBASE
+ Offset
Mnemonic Register Name Default Access
00h–03h GPIO_USE_SEL GPIO Use Select B96BA1FF R/W
04h–07h GP_IO_SEL GPIO Input/Output Select F6FF6EFFh R/W
08h–0Bh — Reserved 0h —
0Ch–0Fh GP_LVL GPIO Level for Input or Output 02FE0100h R/W
10h–13h — Reserved 0h —
14h–17h — Reserved 0h —
18h–1Bh GPO_BLINK GPIO Blink Enable 00040000h R/W
1Ch–1Fh GP_SER_BLINK GP Serial Blink 00000000h R/W
20–23h GP_SB_CMDSTS GP Serial Blink Command Status 00080000h R/W
24–27h GP_SB_DATA GP Serial Blink Data 00000000h R/W
28–29h GPI_NMI_EN GPI NMI Enable 0000 R/W
2A–2Bh GPI_NMI_STS GPI NMI Status 0000 R/WC
2C–2Fh GPI_INV GPIO Signal Invert 00000000h R/W
30h–33h GPIO_USE_SEL2 GPIO Use Select 2
020300FEh
(mobile only) /
020300FFh
(Desktop only)
R/W
34h–37h GP_IO_SEL2 GPIO Input/Output Select 2 1F57FFF4h R/W
38h–3Bh GP_LVL2 GPIO Level for Input or Output 2 A4AA0007h R/W
3Ch–3Fh — Reserved 0h —
40h–43h GPIO_USE_SEL3 GPIO Use Select 3
00000030h
(mobile only)/
00000130h
(desktop only)
R/W
44h–47h GPIO_SEL3 GPIO Input/Output Select 3 00000F00h R/W
48h–4Bh GP_LVL3 GPIO Level for Input or Output 3 000000C0h R/W
4Ch–5Fh — Reserved 0h —
60h–63h GP_RST_SEL[31:0] GPIO Reset Select 1 01000000h R/W
64h–67h GP_RST_SEL[63:32] GPIO Reset Select 2 0h R/W
68h–6Bh GP_RST_SEL[95:64] GPIO Reset Select 3 0h R/W
6Ch–7Fh — Reserved 0h —