LPC Interface Bridge Registers (D31:F0)
540 Datasheet
13.9.9 TCO_WDCNT—TCO Watchdog Control Register
Offset Address: TCOBASE + 0Eh Attribute: R/W
Default Value: 00h Size: 8 bits
Power Well: Resume
13.9.10 SW_IRQ_GEN—Software IRQ Generation Register
Offset Address: TCOBASE + 10h Attribute: R/W
Default Value: 03h Size: 8 bits
Power Well: Core
13.9.11 TCO_TMR—TCO Timer Initial Value Register
I/O Address: TCOBASE +12h Attribute: R/W
Default Value: 0004h Size: 16-bit
Lockable: No Power Well: Core
Bit Description
7:0
The BIOS or system management software can write into this register to indicate more
details on the boot progress. The register will reset to 00h based on a RSMRST# (but
not PLTRST#). The external microcontroller can read this register to monitor boot
progress.
Bit Description
7:2 Reserved
1
IRQ12_CAUSE — R/W. When software sets this bit to 1, IRQ12 will be asserted. When
software sets this bit to 0, IRQ12 will be deasserted.
0
IRQ1_CAUSE — R/W. When software sets this bit to 1, IRQ1 will be asserted. When
software sets this bit to 0, IRQ1 will be deasserted.
Bit Description
15:10 Reserved
9:0
TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the
TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not
be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows
timeouts ranging from 1.2 second to 613.8 seconds.
NOTE: The timer has an error of ±1 tick (0.6 S).
The TCO Timer will only count down in the S0 state.
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