Electrical Characteristics
328 Datasheet
1
Table 8-29. Intel
®
High Definition Audio Timing
Sym Parameter Min Max Units Notes Fig
t143
Time duration for which HDA_SD is
valid before HDA_BCLK edge.
7— ns 8-23
t144
Time duration for which HDA_SDO is
valid after HDA_BCLK edge.
7— ns 8-23
t145
Setup time for HDA_SDIN[3:0] at rising
edge of HDA_BCLK
15 — ns 8-23
t146
Hold time for HDA_SDIN[3:0] at rising
edge of HDA_BCLK
0— ns 8-23
Table 8-30. LPC Timing
Sym Parameter Min Max Units Notes Fig
t150
LAD[3:0] Valid Delay from PCICLK
Rising
211 ns 8-12
t151
LAD[3:0] Output Enable Delay from
PCICLK Rising
2— ns 8-16
t152
LAD[3:0] Float Delay from PCICLK
Rising
—28 ns 8-14
t153 LAD[3:0] Setup Time to PCICLK Rising 7 — ns 8-13
t154 LAD[3:0] Hold Time from PCICLK Rising 0 — ns 8-13
t155
LDRQ[1:0]# Setup Time to PCICLK
Rising
12 — ns 8-13
t156
LDRQ[1:0]# Hold Time from PCICLK
Rising
0— ns 8-13
t157 eE# Valid Delay from PCICLK Rising 2 12 ns 8-12
Table 8-31. Miscellaneous Timings
Sym Parameter Min Max Units Notes Fig
t160 SERIRQ Setup Time to PCICLK Rising 7 — ns 8-13
t161 SERIRQ Hold Time from PCICLK Rising 0 — ns 8-13
t162 RI#, GPIO, USB Resume Pulse Width 2 — RTCCLK 8-15
t163 SPKR Valid Delay from OSC Rising — 200 ns 8-12
t164 SERR# Active to NMI Active — 200 ns
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