Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

32 Datasheet
Figures
2-1 PCH Interface Signals Block Diagram (not all signals are on all SKUs)..........................54
2-2 Example External RTC Circuit.................................................................................91
5-1 Generation of SERR# to Platform .........................................................................120
5-2 LPC Interface Diagram........................................................................................129
5-3 PCH DMA Controller............................................................................................134
5-4 DMA Request Assertion through LDRQ# ................................................................137
5-5 TCO Legacy/Compatible Mode SMBus Configuration................................................184
5-6 Advanced TCO Mode...........................................................................................185
5-7 Serial Post over GPIO Reference Circuit.................................................................187
5-8 Flow for Port Enable / Device Present Bits..............................................................195
5-9 Serial Data transmitted over the SGPIO Interface...................................................199
5-10 EHCI with USB 2.0 with Rate Matching Hub ...........................................................214
5-11 Flash Descriptor Sections ....................................................................................245
5-12 Analog Port Characteristics..................................................................................254
5-13 LVDS Signals and Swing Voltage ..........................................................................256
5-14 LVDS Clock and Data Relationship........................................................................256
5-15 Panel Power Sequencing .....................................................................................257
5-16 HDMI Overview..................................................................................................258
5-17 DP Overview......................................................................................................259
5-18 SDVO Conceptual Block Diagram..........................................................................261
6-1 Desktop PCH Ballout (Top View - Upper Left) .........................................................268
6-2 Desktop PCH Ballout (Top View - Lower Left) .........................................................269
6-3 Desktop PCH Ballout (Top View - Upper Right) .......................................................270
6-4 Desktop PCH Ballout (Top View - Lower Right) .......................................................271
6-5 Mobile PCH Ballout (Top View - Upper Left)............................................................280
6-6 Mobile PCH Ballout (Top View - Lower Left)............................................................281
6-7 Mobile PCH Ballout (Top View - Upper Right)..........................................................282
6-8 Mobile PCH Ballout (Top View - Lower Right)..........................................................283
7-1 Desktop PCH Package Drawing.............................................................................294
7-2 Mobile PCH Package Drawing ...............................................................................296
8-1 G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram.......................334
8-2 G3 w/RTC Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram ..................334
8-3 S5 to S0 Timing Diagram ....................................................................................335
8-4 S3/M3 to S0 Timing Diagram...............................................................................336
8-5 S5/Moff - S5/M3 Timing Diagram .........................................................................336
8-6 S0 to S5 Timing Diagram ....................................................................................337
8-7 S4/S5 to Deep S4/S5 to G3 w/ RTC Loss Timing Diagram........................................338
8-8 DRAMPWROK Timing Diagram..............................................................................338
8-9 Clock Cycle Time................................................................................................339
8-10 Transmitting Position (Data to Strobe) ..................................................................339
8-11 Clock Timing......................................................................................................339
8-13 Setup and Hold Times.........................................................................................340
8-14 Float Delay........................................................................................................340
8-15 Pulse Width.......................................................................................................340
8-12 Valid Delay from Rising Clock Edge.......................................................................340
8-16 Output Enable Delay...........................................................................................341
8-17 USB Rise and Fall Times......................................................................................341
8-18 USB Jitter .........................................................................................................341
8-19 USB EOP Width..................................................................................................342
8-20 SMBus Transaction.............................................................................................342
8-21 SMBus Timeout..................................................................................................342
8-22 SPI Timings.......................................................................................................343
8-23 Intel
®
High Definition Audio Input and Output Timings............................................343
8-24 Dual Channel Interface Timings............................................................................344
8-25 Dual Channel Interface Timings............................................................................344
8-26 LVDS Load and Transition Times ..........................................................................344
8-27 Transmitting Position (Data to Strobe) ..................................................................345
8-28 PCI Express Transmitter Eye................................................................................345
8-29 PCI Express Receiver Eye....................................................................................346
8-30 Measurement Points for Differential Waveforms......................................................347
8-31 PCH Test Load ...................................................................................................348
8-32 Controller Link Receive Timings............................................................................348
8-33 Controller Link Receive Slew Rate........................................................................348

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General

Brand	Intel
Model	6 SERIES CHIPSET - DATASHEET 01-2011
Category	Controller
Language	English