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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
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Functional Description
154 Datasheet
5.10.5 Data Frame Format
Table 5-20 shows the format of the data frames. For the PCI interrupts (A–D), the
output from the PCH is AND’d with the PCI input signal. This way, the interrupt can be
signaled using both the PCI interrupt input signal and using the SERIRQ signal (they
are shared).
Table 5-20. Data Frame Format
Data
Frame
#
Interrupt
Clocks Past
Start
Frame
Comment
1IRQ0 2
Ignored. IRQ0 can only be generated using the internal
8524
2IRQ1 5
3 SMI# 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.
4IRQ3 11
5IRQ4 14
6IRQ5 17
7IRQ6 20
8IRQ7 23
9 IRQ8 26 Ignored. IRQ8# can only be generated internally.
10 IRQ9 29
11 IRQ10 32
12 IRQ11 35
13 IRQ12 38
14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR#
15 IRQ14 44 Not attached to SATA logic
16 IRQ15 47 Not attached to SATA logic
17 IOCHCK# 50 Same as ISA IOCHCK# going active.
18 PCI INTA# 53 Drive PIRQA#
19 PCI INTB# 56 Drive PIRQB#
20 PCI INTC# 59 Drive PIRQC#
21 PCI INTD# 62 Drive PIRQD#

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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General IconGeneral
BrandIntel
Model6 SERIES CHIPSET - DATASHEET 01-2011
CategoryController
LanguageEnglish

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