Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Port [5:0] DMA Register Address Map

Datasheet 599
SATA Controller Registers (D31:F2)
14.4.2 Port Registers (D31:F2)
Ports not available will result in the corresponding Port DMA register space being
reserved. The controller shall ignore writes to the reserved space on write cycles and
shall return 0 on read cycle accesses to the reserved location.
Table 14-5. Port [5:0] DMA Register Address Map (Sheet 1 of 3)
ABAR +
Offset
Mnemonic Register
100h–103h P0CLB Port 0 Command List Base Address
104h–107h P0CLBU Port 0 Command List Base Address Upper 32-Bits
108h–10Bh P0FB Port 0 FIS Base Address
10Ch–10Fh P0FBU Port 0 FIS Base Address Upper 32-Bits
110h–113h P0IS Port 0 Interrupt Status
114h–117h P0IE Port 0 Interrupt Enable
118h–11Bh P0CMD Port 0 Command
11Ch–11Fh — Reserved
120h–123h P0TFD Port 0 Task File Data
124h–127h P0SIG Port 0 Signature
128h–12Bh P0SSTS Port 0 Serial ATA Status
12Ch–12Fh P0SCTL Port 0 Serial ATA Control
130h–133h P0SERR Port 0 Serial ATA Error
134h–137h P0SACT Port 0 Serial ATA Active
138h–13Bh P0CI Port 0 Command Issue
13Ch–17Fh — Reserved
180h–183h P1CLB Port 1 Command List Base Address
184h–187h P1CLBU Port 1 Command List Base Address Upper 32-Bits
188h–18Bh P1FB Port 1 FIS Base Address
18Ch–18Fh P1FBU Port 1 FIS Base Address Upper 32-Bits
190h–193h P1IS Port 1 Interrupt Status
194h–197h P1IE Port 1 Interrupt Enable
198h–19Bh P1CMD Port 1 Command
19Ch–19Fh — Reserved
1A0h–1A3h P1TFD Port 1 Task File Data
1A4h–1A7h P1SIG Port 1 Signature
1A8h–1ABh P1SSTS Port 1 Serial ATA Status
1ACh–1AFh P1SCTL Port 1 Serial ATA Control
1B0h–1B3h P1SERR Port 1 Serial ATA Error
1B4h–1B7h P1SACT Port 1 Serial ATA Active
1B8h–1BBh P1CI Port 1 Command Issue
1BCh–1FFh — Reserved