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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
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Electrical Characteristics
314 Datasheet
8.6 AC Characteristics
NOTES:
1. Specified at the measurement point into a timing and voltage compliance test load and
measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye
diagram)
2. A T
TX-EYE
= 0.70 UI provides for a total sum of deterministic and random jitter budget of
T
TXJITTER-MAX
= 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The
T
TXEYE-MEDIAN-to-MAX-JITTER
specification ensures a jitter distribution in which the median
and the maximum deviation from the median is less than half of the total TX jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value.
3. Specified at the measurement point and measured over any 250 consecutive UIs. The test
load documented in the PCI Express* specification 2.0 should be used as the RX device
when taking measurements (also refer to the Receiver compliance eye diagram). If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
4. A T
RX-EYE
= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter
budget for the Transmitter and interconnect collected any 250 consecutive UIs. The T
RX-
EYE-MEDIAN-to--MAX-JITTER
specification ensures a jitter distribution in which the median and
the maximum deviation from the median is less than half of the total 0.6 UI jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
5. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s.
Table 8-16. PCI Express* Interface Timings
Symbol Parameter Min Max Unit Figures Notes
Transmitter and Receiver Timings
UI
Unit Interval – PCI Express*
Gen 1 (2.5 GT/s)
399.88 400.12 ps 5
UI
Unit Interval – PCI Express*
Gen 2 (5.0 GT/s)
199.9 200.1 ps 5
T
TX-EYE
Minimum Transmission Eye
Width
0.7 UI 8-28 1,2
T
TX-RISE/Fall
(Gen1)
D+/D- TX Out put Rise/Fall
time
—0.125 UI 1,2
T
TX-RISE/Fall
(Gen2)
D+/D- TX Out put Rise/Fall
time
—0.15 UI 1,2
T
RX-EYE
Minimum Receiver Eye Width 0.40 UI 8-29 3,4

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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General IconGeneral
BrandIntel
Model6 SERIES CHIPSET - DATASHEET 01-2011
CategoryController
LanguageEnglish

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