Functional Description
256 Datasheet
Logic values of 1s and 0s are represented by the differential voltage between the pair
of signals. As shown in the Figure 5-14 a serial pattern of 1100011 represents one
cycle of the clock.
5.26.2.1.1 LVDS Pair States
The LVDS pairs can be put into one of five states:
•Active
•Powered down Hi-Z
• Powered down 0 V
•Common mode
•Send zeros
When in the active state, several data formats are supported. When in powered down
state, the circuit enters a low power state and drives out 0 V or the buffer is the Hi-Z
state on both the output pins for the entire channel. The common mode Hi-Z state is
both pins of the pair set to the common mode voltage. When in the send zeros state,
the circuit is powered up but sends only zero for the pixel color data regardless what
the actual data is with the clock lines and timing signals sending the normal clock and
timing data.
The LVDS Port can be enabled/disabled using software. A disabled port enters a low
power state. Once the port is enabled, individual driver pairs may be disabled based on
the operating mode. Disabled drivers can be powered down for reduced power
consumption or optionally fixed to forced 0s output.
Individual pairs or sets of LVDS pairs can be selectively powered down when not being
used. The panel power sequencing can be set to override the selected power state of
the drivers during power sequencing.
Figure 5-13. LVDS Signals and Swing Voltage
Figure 5-14. LVDS Clock and Data Relationship
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