Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 359
Chipset Configuration Registers
10 Chipset Configuration Registers
This section describes all registers and base functionality that is related to chipset
configuration and not a specific interface (such as LPC, PCI, or PCI Express*). It
contains the root complex register block, which describes the behavior of the upstream
internal link.
This block is mapped into memory space, using the Root Complex Base Address (RCBA)
register of the PCI-to-LPC bridge. Accesses in this space must be limited to 32-(DW) bit
quantities. Burst accesses are not allowed.
All Chipset Configuration Registers are located in the core well unless otherwise
indicated.
10.1 Chipset Configuration Registers (Memory Space)
Note: Address locations that are not shown should be treated as Reserved (see Section 9.2
for details).
.
Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 4)
Offset Mnemonic Register Name Default Type
0050h–0053h CIR0 Chipset Initialization Register 0 00000000h R/WL
0400h–0403 RPC Root Port Configuration 0000000yh R/W, RO
0404h–0407h RPFN
Root Port Function Number and Hide
for PCI Express Root Ports
76543210h
R/WO,
RO
0408h–040B FLRSTAT
Function Level Reset Pending Status
Summary
00000000h RO
0900h–0901h CIR2 Chipset Initialization Register 2 0000h R/W
1100h–1101h CIR3 Chipset Initialization Register 3 0000h R/W
1E00h–1E03h TRSR Trap Status Register 00000000h
R/WC,
RO
1E10h–1E17h TRCR Trapped Cycle Register
000000000000
0000h
RO
1E18h–1E1Fh TWDR Trapped Write Data Register
000000000000
0000h
RO
1E80h–1E87h IOTR0 I/O Trap Register 0
000000000000
0000h
R/W
1E88h–1E8Fh IOTR1 I/O Trap Register 1
000000000000
0000h
R/W
1E90h–1E97h IOTR2 I/O Trap Register 2
000000000000
0000h
R/W
1E98h–1E9Fh IOTR3 I/O Trap Register 3
000000000000
0000h
R/W
2014h–2017h V0CTL VC 0 Resource Control 80000011h
R/WL,
RO
201Ah–201Bh V0STS VC 0 Resource Status 0000h RO