Chipset Configuration Registers
360 Datasheet
2020h–2023h V1CTL VC 1 Resource Control 00000000h
R/W, RO,
R/WL
2026h–2027h V1STS VC 1 Resource Status 0000h RO
2030h–2033h CIR31 Chipset Initialization Register 31 00000000h
R/WL.
RO
2040h–2043h CIR32 Chipset Initialization Register 32 00000000h
R/WL.
RO
2088h–208Bh CIR1 Chipset Initialization Register 1 00000000h R/WO
20ACh–20AFh REC Root Error Command 0000h R/W
21A4h–21A7h LCAP Link Capabilities 00012C42h
RO, R/
WO
21A8h–21A9h LCTL Link Control 0000h R/W
21AAh–21ABh LSTS Link Status 0042h RO
2234h–2327h DMIC DMI Control 00000000h R/W, RO
2238h–223Bh CIR30 Chipset Initialization Register 30 00000000h R/W
228Ch–228Fh CIR5 Chipset Initialization Register 5 00000000h R/W
2304h–2307h DMC DMI Miscellaneous Control Register 00000000h R/W
2314h–2317h CIR6
CIR6—Chipset Initialization Register
6
0A000000h R/W
2320h–2323h CIR9 Chipset Initialization Register 9 00000000h R/W
3000h–3000h TCTL TCO Configuration 00h R/W
3100h–3103h D31IP Device 31 Interrupt Pin 03243200h R/W, RO
3104h–3107h D30IP Device 30 Interrupt Pin 00000000h RO
3108h–310Bh D29IP Device 29 Interrupt Pin 10004321h R/W
310Ch–310Fh D28IP Device 28 Interrupt Pin 00214321h R/W
3110h–3113h D27IP Device 27 Interrupt Pin 00000001h R/W
3114h–3117h D26IP Device 26 Interrupt Pin 30000321h R/W
3118h–311Bh D25IP Device 25 Interrupt Pin 00000001h R/W
3124h–3127h D22IP Device 22 Interrupt Pin 00000001h R/W
3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W
3142h–3143h D30IR Device 30 Interrupt Route 0000h RO
3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W
3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W
3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W
314Ch–314Fh D26IR Device 26 Interrupt Route 3210h R/W
3150h–3153h D25IR Device 25 Interrupt Route 3210h R/W
315Ch–316Fh D22IR Device 22 Interrupt Route 3210h R/W
31FEh–31FFh OIC Other Interrupt Control 0000h R/W
3310h–3313h PRSTS Power and Reset Status 03000000h
RO, R/
WC
Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 4)
Offset Mnemonic Register Name Default Type
To Next Page
Loading...