Functional Description
242 Datasheet
5.23 Intel
®
ME and Intel
®
ME Firmware 7.0
Intel ME is a platform-level solution that utilizes multiple system components including:
• The Intel ME is the general purpose controller that resides in the PCH. It operates in
parallel to and is resource-isolated from the host processor.
• The flash device stores Intel ME Firmware code that is executed by the Intel ME for
its operations. In M0, the highest power state, this code is loaded from flash into
DRAM and cached in secure and isolated SRAM. Code that resides in DRAM is
stored in 16 MB of unified memory architecture (UMA) memory taken off the
highest order rank in channel 0. The PCH controls the flash device through the SPI
interface and internal logic.
• In order to interface with DRAM, the Intel ME utilizes the integrated memory
controller (IMC) present in the processor. DMI serves as the interface for
communication between the IMC and Intel ME. This interfacing occurs in only M0
power state. In the lower ME power state, M3, code is executed exclusively from
secure and isolated Intel ME local RAM.
5.24 Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost
alternative for system flash versus the Firmware Hub on the LPC bus.
The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In
(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select
(SPI_CS[1:0]#).
The PCH supports up to two SPI flash devices using two separate Chip Select pins. Each
SPI flash device can be up to 16 MB. The PCH SPI interface supports 20-MHz, 33-MHz,
and 50-MHz SPI devices. A SPI Flash device on with Chip Select 0 with a valid
descriptor MUST be attached directly to the PCH.
Communication on the SPI bus is done with a Master – Slave protocol. The Slave is
connected to the PCH and is implemented as a tri-state bus.
Note: If Boot BIOS Strap =’00’ LPC is selected as the location for BIOS. BIOS may still be
placed on LPC, but all platforms with the PCH requires SPI flash connected directly to
the PCH's SPI bus with a valid descriptor connected to Chip Select 0 in order to boot.
Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected
by the PCH, LPC based BIOS flash is disabled.
5.24.1 SPI Supported Feature Overview
SPI Flash on the PCH has two operational modes, descriptor and non-descriptor.
5.24.1.1 Non-Descriptor Mode
Non-Descriptor Mode is not supported as a valid flash descriptor is required for all PCH
Platforms.
To Next Page
Loading...
Need help?
General
