Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Enhanced Host Controller Operational Register Address Map

EHCI Controller Registers (D29:F0, D26:F0)
664 Datasheet
16.2.2 Host Controller Operational Registers
This section defines the enhanced host controller operational registers. These registers
are located after the capabilities registers. The operational register base must be
DWord-aligned and is calculated by adding the value in the first capabilities register
(CAPLENGTH) to the base address of the enhanced host controller register address
space (MEM_BASE). Since CAPLENGTH is always 20h, Table 16-3 already accounts for
this offset. All registers are 32 bits in length.
Note: Software must read and write these registers using only DWord accesses.These
registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are
implemented in the core power well. Unless otherwise noted, the core well registers are
reset by the assertion of any of the following:
• Core well hardware reset
• HCRESET
•D3-to-D0 reset
Table 16-3. Enhanced Host Controller Operational Register Address Map
MEM_BASE
+ Offset
Mnemonic Register Name Default
Special
Notes
Type
20h–23h USB2.0_CMD USB 2.0 Command 00080000h R/W, RO
24h–27h USB2.0_STS USB 2.0 Status 00001000h R/WC, RO
28h–2Bh USB2.0_INTR USB 2.0 Interrupt Enable 00000000h R/W
2Ch–2Fh FRINDEX USB 2.0 Frame Index 00000000h R/W,
30h–33h CTRLDSSEGMENT Control Data Structure Segment 00000000h R/W, RO
34h–37h PERODICLISTBASE Period Frame List Base Address 00000000h R/W
38h–3Bh ASYNCLISTADDR
Current Asynchronous List
Address
00000000h R/W
3Ch–5Fh — Reserved 0h RO
60h–63h CONFIGFLAG Configure Flag 00000000h Suspend R/W
64h–67h PORT0SC Port 0 Status and Control 00003000h Suspend
R/W,
R/WC, RO
68h–6Bh PORT1SC Port 1 Status and Control 00003000h Suspend
R/W,
R/WC, RO
6Ch–6Fh PORT2SC Port 2 Status and Control 00003000h Suspend
R/W,
R/WC, RO
70h–73h PORT3SC Port 3 Status and Control 00003000h Suspend
R/W,
R/WC, RO
74h–77h PORT4SC Port 4 Status and Control 00003000h Suspend
R/W,
R/WC, RO
78h–7Bh PORT5SC Port 5 Status and Control 00003000h Suspend
R/W,
R/WC, RO
74h–77h
(D29 Only)
PORT6SC Port 6 Status and Control 00003000h Suspend
R/W,
R/WC, RO
78h–7Bh
(D29 Only)
PORT7SC Port 7 Status and Control 00003000h Suspend
R/W,
R/WC, RO
7Ch–9Fh — Reserved Undefined RO
A0h–B3h — Debug Port Registers Undefined
See
register
description
B4h–3FFh — Reserved Undefined RO