Datasheet 809
Serial Peripheral Interface (SPI)
21 Serial Peripheral Interface
(SPI)
The Serial Peripheral Interface resides in memory mapped space. This function contains
registers that allow for the setup and programming of devices that reside on the SPI
interface.
Note: All registers in this function (including memory-mapped registers) must be addressable
in byte, word, and DWord quantities. The software must always make register accesses
on natural boundaries (that is, DWord accesses must be on DWord boundaries; word
accesses on word boundaries, etc.) In addition, the memory-mapped register space
must not be accessed with the LOCK semantic exclusive-access mechanism. If software
attempts exclusive-access mechanisms to the SPI memory-mapped space, the results
are undefined.
21.1 Serial Peripheral Interface Memory Mapped
Configuration Registers
The SPI Host Interface registers are memory-mapped in the RCRB (Root Complex
Register Block) Chipset Register Space with a base address (SPIBAR) of 3800h and are
located within the range of 3800h to 39FFh. The address for RCRB can be found in
RCBA Register see Section 13.1.37. The individual registers are then accessible at
SPIBAR + Offset as indicated in the following table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Table 21-1. Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) (Sheet 1 of 2)
SPIBAR +
Offset
Mnemonic Register Name Default
00h–03h BFPR BIOS Flash Primary Region 00000000h
04h–05h HSFSTS Hardware Sequencing Flash Status 0000h
06h–07h HSFCTL Hardware Sequencing Flash Control 0000h
08h–0Bh FADDR Flash Address 00000000h
0Ch–0Fh Reserved Reserved 00000000h
10h–13h FDATA0 Flash Data 0 00000000h
14h–4Fh FDATAN Flash Data N 00000000h
50h–53h FRACC Flash Region Access Permissions 00000202h
54h–57h FREG0 Flash Region 0 00000000h
58h–5Bh FREG1 Flash Region 1 00000000h
5Ch–5F FREG2 Flash Region 2 00000000h
60h–63h FREG3 Flash Region 3 00000000h
64h–67h FREG3 Flash Region 4 00000000h
67h–73h Reserved Reserved for Future Flash Regions
74h–77h FPR0 Flash Protected Range 0 00000000h
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