Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - G3 WRtc Loss to S4 S5 (with Deep S4 S5 Support) Timing Diagram; G3 WRtc Loss to S4 S5 (Without Deep S4 S5 Support) Timing Diagram

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Electrical Characteristics

334 Datasheet

8.8 Power Management Timing Diagrams

Figure 8-1. G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram

Signal NameDestinationSource

SUSCLK

RSMRST#

Board PCH

Board

VccRTCBoard PCH

RTCRST#Board PCH

t200

VccSusBoard PCH

t201

SLP_S5#PCH Board

Only for S4 after G 3 or DeepS x

VccDSW3_3Board PCH

DPWROKBoard PCH

t200b

t200c

Deep S4/S5

t202

valid

S5/S4

PCH

t200a

t202a

t225

t226

SLP_SUS#PCH Board

Figure 8-2. G3 w/RTC Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram