Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Bus Master IDE I;O Register Address Map

Datasheet 633
SATA Controller Registers (D31:F5)
15.2 Bus Master IDE I/O Registers (D31:F5)
The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR
register, located in Device 31:Function 2 Configuration space, offset 20h. All bus
master IDE I/O space registers can be accessed as byte, word, or DWord quantities.
Reading reserved bits returns an indeterminate, inconsistent value, and writes to
reserved bits have no affect (but should not be attempted). These registers are only
used for legacy operation. Software must not use these registers when running AHCI.
The description of the I/O registers is shown in Table 15-2.
Table 15-2. Bus Master IDE I/O Register Address Map
BAR+
Offset
Mnemonic Register Default Type
00 BMICP Command Register Primary 00h R/W
01 — Reserved — RO
02 BMISP Bus Master IDE Status Register Primary 00h
R/W, R/WC,
RO
03 — Reserved — RO
04–07 BMIDP
Bus Master IDE Descriptor Table Pointer
Primary
xxxxxxxxh R/W
08 BMICS Command Register Secondary 00h R/W
09 — Reserved — RO
0Ah BMISS Bus Master IDE Status Register Secondary 00h
R/W, R/WC,
RO
0Bh — Reserved — RO
0Ch–0Fh BMIDS
Bus Master IDE Descriptor Table Pointer
Secondary
xxxxxxxxh R/W