Datasheet 115
PCH and System Clocks
4.2 Functional Blocks
The PCH has up to 8 PLLs, 4 Spread Modulators, and a numbers of dividers to provide
great flexibility in clock source selection, configuration, and better power management.
Table 4-3 describes the PLLs on the PCH and the clock domains that are driven from the
PLLs.
NOTES:
1. Indicates the source clock frequencies driven to other internal logic for delivering functionality needed.
Does not indicate external outputs
2. Powered in sub-S0 states by a Suspend well Ring oscillator.
Table 4-3. PCH PLLs
PLL Outputs
1
Description/Usage
XCK_PLL
Eight 2.4 GHz 45° phase
shifted. Outputs are routed
to each of the Spread
Modulator blocks before
hitting the various dividers
and the other PLLs to
provide appropriate clocks
to all of the I/O interface
logic.
Main Reference PLL. Always enabled in Integrated
Clocking mode. Resides in core power well and is not
powered in S3 and below states.
DMI_PLL
2.5 GHz/625 MHz/250 MHz
DMI Gen2 clocks
Source clock is 100 MHz from XCK_PLL (post-dividers). It
is the primary PLL resource to generate the DMI port
clocks.
Resides in core power well and is not powered in S3 and
below states.
FDI_PLL
2.7 GHz/270 MHz/450 MHz
FDI logic and link clocks
Source clock is 100 MHz from XCK_PLL (post-dividers).
Resides in the core power well and is not powered in S3
and below states.
PCIEPXP_PLL
2.5 GHz/625 MHz/
500 MHz/250 MHz/125 MHz
clocks for PCI Express* 2.0
interface.
Source clock is from XCK_PLL. PCIEPXP_PLL drives clocks
to PCIe ports and Intel
®
ME engine
2
(in S0 state). Can be
optionally used to supply DMI clocks.
Resides in the core power well and is not powered in S3
and below states.
SATA_PLL
3.0 GHz/1.5 GHz/300 MHz/
150 MHz clocks for SATA
logic (serial clock, Tx/Rx
clocks)
Source clock is 100 MHz from XCK_PLL (post-divider).
This PLL generates all the required SATA Gen2 and SATA
Gen3 clocks.
Resides in core power well and is not powered in S3 and
below states.
USB_PLL
24-/48-/240-/480 MHz
clocks for legacy USB 2.0/
USB 1.0 logic
Source clock is from XCK_PLL (post-divider).
Resides in core power well and is not powered in S3 and
below states.
DPLL_A/B
Runs with a wide variety of
frequency and divider
options.
Source clock is 120 MHz from XCK_PLL (post-divider).
Provides Reference clocks required for Integrated
Graphics Display.
Resides in core power well and is not powered in S3 and
below states.
To Next Page
Loading...