Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Enhanced Host Controller Capability Registers

Datasheet 661
EHCI Controller Registers (D29:F0, D26:F0)
16.2 Memory-Mapped I/O Registers
The EHCI memory-mapped I/O space is composed of two sets of registers—Capability
Registers and Operational Registers.
Note: The PCH EHCI controller will not accept memory transactions (neither reads nor writes)
as a target that are locked transactions. The locked transactions should not be
forwarded to PCI as the address space is known to be allocated to USB.
Note: When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory
range are ignored and result a master abort. Similarly, if the Memory Space Enable
(MSE) bit (D29:F0, D26:F0:04h, bit 1) is not set in the Command register in
configuration space, the memory range will not be decoded by the PCH enhanced host
controller (EHC). If the MSE bit is not set, the PCH must default to allowing any
memory accesses for the range specified in the BAR to go to PCI. This is because the
range may not be valid and, therefore, the cycle must be made available to any other
targets that may be currently using that range.
16.2.1 Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation. Within the host controller capability registers, only the structural
parameters register is writable. These registers are implemented in the suspend well
and is only reset by the standard suspend-well hardware reset, not by HCRESET or the
D3-to-D0 reset.
Note: Note that the EHCI controller does not support as a target memory transactions that
are locked transactions. Attempting to access the EHCI controller Memory-Mapped I/O
space using locked memory transactions will result in undefined behavior.
Note: Note that when the USB2 function is in the D3 PCI power state, accesses to the USB2
memory range are ignored and will result in a master abort. Similarly, if the Memory
Space Enable (MSE) bit is not set in the Command register in configuration space, the
memory range will not be decoded by the Enhanced Host Controller (EHC). If the MSE
bit is not set, the EHC will not claim any memory accesses for the range specified in the
BAR.
NOTE: “Read/Write Special” means that the register is normally read-only, but may be written
when the WRT_RDONLY bit is set. Because these registers are expected to be programmed
by BIOS during initialization, their contents must not get modified by HCRESET or D3-to-
D0 internal reset.
Table 16-2. Enhanced Host Controller Capability Registers
MEM_BASE
+ Offset
Mnemonic Register Default Type
00h CAPLENGTH Capabilities Registers Length 20h RO
02h–03h HCIVERSION
Host Controller Interface Version
Number
0100h RO
04h–07h HCSPARAMS
Host Controller Structural
Parameters
00204208h
(D29:F0)
00203206
(D26:F0)
R/W
(special), RO
08h–0Bh HCCPARAMS
Host Controller Capability
Parameters
00006881h RO