EasyManua.ls Logo

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Analog Display;VGA DAC Signals; Analog Display Interface Signals

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
936 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Datasheet 75
Signal Description
2.21 Analog Display /VGA DAC Signals
L_VDD_EN (available
in Desktop)
O
LVDS Panel Power Enable: Panel power control enable
control for LVDS or embedded DisplayPort*.
This signal is also called VDD_DBL in the CPIS specification
and is used to control the VDC source to the panel logic.
L_BKLTEN (available in
Desktop)
O
LVDS Backlight Enable: Panel backlight enable control for
LVDS or embedded DisplayPort.
This signal is also called ENA_BL in the CPIS specification
and is used to gate power into the backlight circuitry.
L_BKLTCTL (available
in Desktop)
O
Panel Backlight Brightness Control: Panel brightness
control for LVDS or embedded DisplayPort.
This signal is also called VARY_BL in the CPIS specification
and is used as the PWM Clock input signal.
LVDS_VREFH O Test mode voltage reference.
LVDS_VREFL O Test mode voltage reference.
LVD_IBG I LVDS reference current.
LVD_VBG O Test mode voltage reference.
Table 2-21. Analog Display Interface Signals
Name Type Description
VGA_RED
O
A
RED Analog Video Output: This signal is a VGA Analog video
output from the internal color palette DAC.
VGA_GREEN
O
A
GREEN Analog Video Output: This signal is a VGA Analog
video output from the internal color palette DAC.
VGA_BLUE
O
A
BLUE Analog Video Output: This signal is a VGA Analog video
output from the internal color palette DAC.
DAC_IREF
I/O
A
Resistor Set: Set point resistor for the internal color palette
DAC. A 1 k 1% resistor is required between DAC_IREF and
motherboard ground.
VGA_HSYNC
O
HVCMOS
VGA Horizontal Synchronization: This signal is used as the
horizontal sync (polarity is programmable) or “sync interval”. 2.5
V output
VGA_VSYNC
O
HVCMOS
VGA Vertical Synchronization: This signal is used as the
vertical sync (polarity is programmable). 2.5 V output.
VGA_DDC_CLK
I/O
COD
Monitor Control Clock
VGA_DDC_DATA
I/O
COD
Monitor Control Data
VGA_IRTN
I/O
COD
Monitor Interrupt Return
Table 2-20. LVDS Interface Signals (Sheet 2 of 2)
Name Type Description

Table of Contents

Related product manuals