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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
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Datasheet 95
PCH Pin States
3.2 Output and I/O Signals Planes and States
Table 3.2 and Table 3-3 shows the power plane associated with the output and I/O
signals, as well as the state at various times. Within the table, the following terms are
used:
“High-Z” Tri-state. PCH not driving the signal high or low.
“High” PCH is driving the signal to a logic 1.
“Low” PCH is driving the signal to a logic 0.
“Defined” Driven to a level that is defined by the function or external pull-
up/pull-down resistor (will be high or low).
“Undefined” PCH is driving the signal, but the value is indeterminate.
“Running” Clock is toggling or signal is transitioning because function not
stopping.
“Off” The power plane is off; PCH is not driving when configured as an
output or sampling when configured as an input.
“Input” PCH is sampling and signal state determined by external driver.
Note: Signal levels are the same in S4 and S5, except as noted.
PCH suspend well signal states are indeterminate and undefined and may glitch prior to
RSMRST# deassertion. This does not apply to SLP_S3#, SLP_S4#, and SLP_S5#.
These signals are determinate and defined prior to RSMRST# deassertion.
PCH core well signal states are indeterminate and undefined and may glitch prior to
PWROK assertion. This does not apply to THRMTRIP#. This signal is determinate and
defined prior to PWROK assertion.
DSW indicates PCH Deep S4/S5 Well. This state provides a few wake events and critical
context to allow system to draw minimal power in S4 or S5 states.
ASW indicates PCH Active Sleep Well. This power well contains functionality associated
with active usage models while the host system is in Sx.
Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 1 of 6)
Signal Name
Power
Plane
During
Reset
1
Immediately
after Reset
1
S0/S1 S3 S4/S5
PCI Express*
PETp[8:1], PETn[8:1] Core Low Low
4
Defined OFF OFF
DMI
DMI[3:0]TXP,
DMI[3:0]TXN
Core Low Low Defined Off Off
PCI Bus
AD[31:0] Core Low Low Low Off Off
C/BE[3:0]# Core Low Low Low Off Off
DEVSEL# Core High-Z High-Z High-Z Off Off

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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General IconGeneral
BrandIntel
Model6 SERIES CHIPSET - DATASHEET 01-2011
CategoryController
LanguageEnglish

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