Functional Description
150 Datasheet
5.9 Advanced Programmable Interrupt Controller
(APIC) (D31:F0)
In addition to the standard ISA-compatible PIC described in the previous chapter, the
PCH incorporates the APIC. While the standard interrupt controller is intended for use
in a uni-processor system, APIC can be used in either a uni-processor or multi-
processor system.
5.9.1 Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through
memory writes on the normal data path to the processor, and interrupts are
handled without the need for the processor to run an interrupt acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 can be given a higher priority than
interrupt 3.
• More Interrupts. The I/O APIC in the PCH supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O
APIC devices in the system with their own interrupt vectors.
5.9.2 Interrupt Mapping
The I/O APIC within the PCH supports 24 APIC interrupts. Each interrupt has its own
unique vector assigned by software. The interrupt vectors are mapped as follows, and
match “Config 6” of the Multi-Processor Specification.
Table 5-18. APIC Interrupt Mapping
1
(Sheet 1 of 2)
IRQ #
Using
SERIRQ
Direct
from Pin
Using PCI
Message
Internal Modules
0 No No No Cascade from 8259 #1
1Yes No Yes
2 No No No 8254 Counter 0, HPET #0 (legacy mode)
3Yes No Yes
4Yes No Yes
5Yes No Yes
6Yes No Yes
7Yes No Yes
8No No NoRTC, HPET #1 (legacy mode)
9 Yes No Yes Option for SCI, TCO
10 Yes No Yes Option for SCI, TCO
11 Yes No Yes HPET #2, Option for SCI, TCO (Note2)
12 Yes No Yes HPET #3 (Note 3)
13 No No No FERR# logic
14 Yes No Yes SATA Primary (legacy mode)
15 Yes No Yes SATA Secondary (legacy mode)
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