LPC Interface Bridge Registers (D31:F0)
506 Datasheet
13.8 Power Management Registers
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicated, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
13.8.1 Power Management PCI Configuration Registers
(PM—D31:F0)
Table 13-9 shows a small part of the configuration space for PCI Device 31: Function 0.
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
Table 13-9. Power Management PCI Register Address Map (PM—D31:F0)
Offset Mnemonic Register Name Default Type
A0h–A1h GEN_PMCON_1
General Power Management
Configuration 1
0000h
R/W, R/WO,
RO
A2h GEN_PMCON_2
General Power Management
Configuration 2
00h
R/W, R/WC,
RO
A4h–A5h GEN_PMCON_3
General Power Management
Configuration 3
4206h R/W, R/WC
A6h
GEN_PMCON_LO
CK
General Power Management
Configuration Lock
00h RO, R/WLO
A9h CIR4 Chipset Initialization Register 4 03h R/W
AA BM_BREAK_EN_2 BM_BREAK_EN Register #2 00h R/W, RO
ABh BM_BREAK_EN BM_BREAK_EN Register 00h R/W
ACh–AFh PMIR Power Management Initialization 00000000h R/W
B8h–BBh GPI_ROUT GPI Route Control 00000000h R/W
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