Electrical Characteristics
336 Datasheet
Figure 8-4. S3/M3 to S0 Timing Diagram
SLP_S3#
SLP_A#
CPU SVID
Signal NameDestSource
SLP_S4#
SLP_S5#
PCH Board
PCH Board
PCH Board
PCH Board
Board PCH
VccCore_CPU
CPU CPU VRM
Board CPU
PROCPWRGD
SUS_STAT#
PWROK
DRAMPWROK
SYS_PWROKCPU VRM PCH
Board PCH
PCH CPU
APWROKBoard PCH
Vcc
Board PCH
25 MHz
Crystal Osc
Board PCH
stable
PLTRST#
DMI
PCH
CPU
PCH
Board
PCH
CPU/Board
PCH
CPU
t205
T
r
a
i
n
i
n
g
S
T
R
A
P
_
S
E
T
C
P
U
_
R
E
S
E
T
_
D
O
N
E
F
l
ex
S
K
U
V
D
M
w
ri
t
e
s
C
P
U
_
R
E
S
E
T
_D
O
N
E
_
A
C
K
t211
t206
Serial VID
Load
Note: V_PROC_IO may go to Vboot at
this time, but can also stay at 0V
(default)
V_vid
PROCPWRGD
t210
SLP_LAN#PCH Board
VccASW
THRMTRIP#
CPU
PCH
ignored honored
Assumes soft strap programmed to start at
CPUPWRGD - expected setting for SNB
stable
PCH
Output Clocks
PCH Board
t209
t208
Figure 8-5. S5/Moff - S5/M3 Timing Diagram
SLP_S3#
SLP_A#
Signal NameDestSource
SLP_S4#
SLP_S5#
PCH Board
PCH Board
PCH Board
PCH Board
Board PCH
APWROKBoard PCH
t207
SLP_LAN#PCH Board
Could already be high before this sequence begins (to
support WOL), but will never go high later than SLP_A#
VccASW
SPI
CL_RST1#
(Mobile Only)
SPI Flash
Controller Link
t212
t213
PCH
PCH
To Next Page
Loading...