Datasheet 207
Functional Description
5.18.7.4 ACPI System States
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
• The System is always in the S0 state when the EHC is in the D0 state. However,
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
• When in D0, the Pause feature (See Section 5.18.7.1) enables dynamic processor
low-power states to be entered.
• The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power
turns off).
• All core well logic is reset in the S3/S4/S5 states.
5.18.8 USB 2.0 Legacy Keyboard Operation
The PCH must support the possibility of a keyboard downstream from either a full-
speed/low-speed or a high-speed port. The description of the legacy keyboard support
is unchanged from USB 1.1.
The EHC provides the basic ability to generate SMIs on an interrupt event, along with
more sophisticated control of the generation of SMIs.
5.18.9 USB 2.0 Based Debug Port
The PCH supports the elimination of the legacy COM ports by providing the ability for
new debugger software to interact with devices on a USB 2.0 port.
High-level restrictions and features are:
• Operational before USB 2.0 drivers are loaded.
• Functions even when the port is disabled.
• Allows normal system USB 2.0 traffic in a system that may only have one USB port.
• Debug Port device (DPD) must be high-speed capable and connect directly to Port 1
and Port 9 on PCH-based systems (such as, the DPD cannot be connected to
Port 1/Port 9 through a hub. When a DPD is detected the PCH EHCI will bypass the
integrated Rate Matching Hub and connect directly to the port and the DPD.).
• Debug Port FIFO always makes forward progress (a bad status on USB is simply
presented back to software).
• The Debug Port FIFO is only given one USB access per microframe.
The Debug port facilitates operating system and device driver debug. It allows the
software to communicate with an external console using a USB 2.0 connection.
Because the interface to this link does not go through the normal USB 2.0 stack, it
allows communication with the external console during cases where the operating
system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is
being debugged. Specific features of this implementation of a debug port are:
• Only works with an external USB 2.0 debug device (console)
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0
power state.
• Capability is interrupted when port is driving USB RESET
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