Datasheet 415
PCI-to-PCI Bridge Registers (D30:F0)
11 PCI-to-PCI Bridge Registers
(D30:F0)
The PCH PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements
the buffering and control logic between PCI and the backbone. The arbitration for the
PCI bus is handled by this PCI device.
11.1 PCI Configuration Registers (D30:F0)
Note: Address locations that are not shown should be treated as Reserved (see Section 9.2
for details).
.
Table 11-1. PCI Bridge Register Address Map (PCI-PCI—D30:F0)
Offset Mnemonic Register Name Default Type
00h–01h VID Vendor Identification 8086h RO
02h–03h DID Device Identification
See register
description
RO
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PSTS PCI Status 0010h R/WC, RO
08h RID Revision Identification
See register
description
RO
09h–0Bh CC Class Code 060401h RO
0Dh PMLT Primary Master Latency Timer 00h RO
0Eh HEADTYP Header Type 01h RO
18h–1Ah BNUM Bus Number 000000h RO
1Bh SMLT Secondary Master Latency Timer 00h R/W
1Ch–1Dh IOBASE_LIMIT I/O Base and Limit 0000h R/W, RO
1Eh–1Fh SECSTS Secondary Status 0280h R/WC, RO
20h–23h
MEMBASE_
LIMIT
Memory Base and Limit 00000000h R/W
24h–27h
PREF_MEM_
BASE_LIMIT
Prefetchable Memory Base and Limit 00010001h R/W, RO
28h–2Bh PMBU32 Prefetchable Memory Upper 32 Bits 00000000h R/W
2Ch–2Fh PMLU32
Prefetchable Memory Limit Upper 32
Bits
00000000h R/W
34h CAPP Capability List Pointer 50h RO
3Ch–3Dh INTR Interrupt Information 0000h R/W, RO
3Eh–3Fh BCTRL Bridge Control 0000h
R/WC, RO,
R/W
40h–41h SPDH Secondary PCI Device Hiding 0000h R/W, RO
44h–47h DTC Delayed Transaction Control 00000000h R/W
48h–4Bh BPS Bridge Proprietary Status 00000000h R/WC, RO
4Ch–4Fh BPC Bridge Policy Configuration 10001200h R/W, RO
50–51h SVCAP Subsystem Vendor Capability Pointer 000Dh RO
54h–57h SVID Subsystem Vendor IDs 00000000 R/WO
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