PCI-to-PCI Bridge Registers (D30:F0)
416 Datasheet
11.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
11.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0)
Offset Address: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.
Bit Description
15:0 Device ID — RO. This is a 16-bit value assigned to the PCI bridge.
Bit Description
15:11 Reserved
10
Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to
disable.
9
Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
8
SERR# Enable (SERR_EN) — R/W.
0 = Disable.
1 = Enable the PCH to generate an NMI (or SMI# if NMI routed to SMI#) when the
D30:F0 SSE bit (offset 06h, bit 14) is set.
7
Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
6
Parity Error Response (PER) — R/W.
0 = The PCH ignores parity errors on the PCI bridge.
1 = The PCH will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are
detected on the PCI bridge.
5
VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
4
Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI
Express* Base Specification, Revision 1.0a
3
Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification.
2
Bus Master Enable (BME) — R/W.
0 = Disable
1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.
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