Datasheet 173
Functional Description
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine
should unconditionally transition to the G2/S5 state, regardless of present state (S0–
S4), even if the PCH PWROK is not active. In this case, the transition to the G2/S5 state
should not depend on any particular response from the processor (such as, a DMI
Messages), nor any similar dependency from any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or
has been released. The status is taken after the de-bounce, and is readable using the
PWRBTN_LVL bit.
Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the
PWRBTN# signal is asserted and held active when the system is in a suspend state
(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0
state, the 4-second timer starts.
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h Bit 3), the Power Button is not a wake event. As a result, it
is conceivable that the user will press and continue to hold the Power Button waiting for
the system to awake. Since a 4-second press of the Power Button is already defined as
an Unconditional Power down, the power button timer will be forced to inactive while
the power-cycle timer is in progress. Once the power-cycle timer has expired, the
Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,
the Power Button must be pressed for another 4 to 5 seconds to create the Override
condition to S5.
Sleep Button
The Advanced Configuration and Power Interface, Version 2.0b defines an optional
Sleep button. It differs from the power button in that it only is a request to go from S0
to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the
Sleep Button cannot.
Although the PCH does not include a specific signal designated as a Sleep Button, one
of the GPIO signals can be used to create a “Control Method” Sleep Button. See the
Advanced Configuration and Power Interface, Version 2.0b for implementation details.
Table 5-34. Transitions Due to Power Button
Present
State
Event Transition/Action Comment
S0/Cx PWRBTN# goes low
SMI or SCI generated
(depending on SCI_EN,
PWRBTN_EN and
GLB_SMI_EN)
Software typically initiates a
Sleep state
S1–S5 PWRBTN# goes low
Wake Event. Transitions to
S0 state
Standard wakeup
G3 PWRBTN# pressed None
No effect since no power
Not latched nor detected
S0–S4
PWRBTN# held low
for at least 4
consecutive seconds
Unconditional transition to
S5 state
No dependence on processor
(DMI Messages) or any other
subsystem
To Next Page
Loading...