Signal Description
74 Datasheet
NOTE:
1. It is highly recommended to prioritize 27/14.318/24/48 MHz clocks on CLKOUTFLEX1 and
CLKOUTFLEX3 outputs. Intel does not recommend configuring the 27/14.318/24/48 MHz
clocks on CLKOUTFLEX0 and CLKOUTFLEX2 if more than 2x 33 MHz clocks in addition to
the Feedback clock are used on the CLKOUT_PCI outputs.
2.20 LVDS Signals
All signals are Mobile Only, except as signals noted otherwise that are available in the
desktop package.
CLKOUTFLEX2
1
/
GPIO66
O
Configurable as a GPIO or as a programmable output clock
which can be configured as one of the following:
• 33 MHz
• 25 MHz
• 27 MHz (SSC/Non-SSC)
• 48/24 MHz
• 14.318 MHz
• DC Output logic ‘0’
CLKOUTFLEX3
1
/
GPIO67
O
Configurable as a GPIO or as a programmable output clock
which can be configured as one of the following:
• 27 MHz (SSC/Non SSC)
• 14.318 MHz output to SIO
• 48/24 MHz (Default)
• DC Output logic ‘0’
XCLK_RCOMP I/O
Differential clock buffer Impedance Compensation:
Connected to an external precision resistor (90.9 ±1%) to
VccDIFFCLKN
Table 2-19. Clock Interface Signals (Sheet 3 of 3)
Name Type Description
Table 2-20. LVDS Interface Signals (Sheet 1 of 2)
Name Type Description
LVDSA_DATA[3:0] O LVDS Channel A differential data output - positive
LVDSA_DATA#[3:0] O LVDS Channel A differential data output - negative
LVDSA_CLK O LVDS Channel A differential clock output - positive
LVDSA_CLK# O LVDS Channel A differential clock output - negative
LVDSB_DATA[3:0] O LVDS Channel B differential data output - positive
LVDSB_DATA#[3:0] O LVDS Channel B differential data output - negative
LVDSB_CLK O LVDS Channel B differential clock output - positive
LVDSB_CLK# O LVDS Channel B differential clock output - negative
L_DDC_CLK I/O EDID support for flat panel display
L_DDC_DATA I/O EDID support for flat panel display
L_CTRL_CLK I/O
Control signal (clock) for external SSC clock chip control –
optional
L_CTRL_DATA I/O
Control signal (data) for external SSC clock chip control –
optional
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