Datasheet 61
Signal Description
2.5 LPC Interface
2.6 Interrupt Interface
NOTE: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be
shared if configured as edge triggered.
Table 2-5. LPC Interface Signals
Name Type Description
LAD[3:0] I/O
LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-
ups are provided.
LFRAME# O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LDRQ0#,
LDRQ1# /
GPIO23
I
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to
request DMA or bus master access. These signals are typically connected
to an external Super I/O device. An internal pull-up resistor is provided on
these signals.
LDRQ1# may optionally be used as GPIO23.
Table 2-6. Interrupt Signals
Name Type Description
SERIRQ I/OD
Serial Interrupt Request: This pin implements the serial interrupt
protocol.
PIRQ[D:A]# I/OD
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in Section 5.8.6. Each PIRQx# line has a separate Route
Control register.
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
legacy interrupts.
These signals are 5 V tolerant.
PIRQ[H:E]# /
GPIO[5:2]
I/OD
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in Section 5.8.6. Each PIRQx# line has a separate Route
Control register.
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
legacy interrupts. If not needed for interrupts, these signals can be
used as GPIO.
These signals are 5 V tolerant.
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