Datasheet 515
LPC Interface Bridge Registers (D31:F0)
13.8.2 APM I/O Decode
Table 13-10 shows the I/O registers associated with APM support. This register space is
enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O location).
13.8.2.1 APM_CNT—Advanced Power Management Control Port Register
I/O Address: B2h Attribute: R/W
Default Value: 00h Size: 8-bit
Lockable: No Usage: Legacy Only
Power Well: Core
13.8.2.2 APM_STS—Advanced Power Management Status Port Register
I/O Address: B3h Attribute: R/W
Default Value: 00h Size: 8-bit
Lockable: No Usage: Legacy Only
Power Well: Core
Table 13-10. APM Register Map
Address Mnemonic Register Name Default Type
B2h APM_CNT Advanced Power Management Control Port 00h R/W
B3h APM_STS Advanced Power Management Status Port 00h R/W
Bit Description
7:0
Used to pass an APM command between the OS and the SMI handler. Writes to this
port not only store data in the APMC register, but also generates an SMI# when the
APMC_EN bit is set.
Bit Description
7:0
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad
register and is not affected by any other register or function (other than a PCI reset).
To Next Page
Loading...