Datasheet 223
Functional Description
NOTE: The external microcontroller is responsible to make sure that it does not update the
contents of the data byte registers until they have been read by the system processor. The
PCH overwrites the old value with any new value received. A race condition is possible
where the new value is being written to the register just at the time it is being read. The
PCH will not attempt to cover this race condition (that is, unpredictable results in this
case).
.
Table 5-48. Slave Write Registers
Register Function
0Command Register. See Table 5-49 for legal values written to this register.
1–3 Reserved
4 Data Message Byte 0
5 Data Message Byte 1
6–7 Reserved
8 Reserved
9–FFh Reserved
Table 5-49. Command Types (Sheet 1 of 2)
Command
Type
Description
0 Reserved
1
WAKE/SMI#. This command wakes the system if it is not already awake. If
system is already awake, an SMI# is generated.
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system
is already awake. The SMI handler should then clear this bit.
2
Unconditional Powerdown. This command sets the PWRBTNOR_STS bit,
and has the same effect as the Powerbutton Override occurring.
3
HARD RESET WITHOUT CYCLING: This command causes a hard reset of the
system (does not include cycling of the power supply). This is equivalent to a
write to the CF9h register with Bits 2:1 set to 1, but Bit 3 set to 0.
4
HARD RESET SYSTEM. This command causes a hard reset of the system
(including cycling of the power supply). This is equivalent to a write to the
CF9h register with Bits 3:1 set to 1.
5
Disable the TCO Messages. This command will disable the PCH from sending
Heartbeat and Event messages (as described in Section 5.14). Once this
command has been executed, Heartbeat and Event message reporting can
only be re-enabled by assertion and deassertion of the RSMRST# signal.
6 WD RELOAD: Reload watchdog timer.
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