Datasheet 151
Functional Description
NOTES:
1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0
through 15 receive active-high internal interrupt sources, while interrupts 16 through 23
receive active-low internal interrupt sources.
2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other
devices to ensure the proper operation of HPET #2. The PCH hardware does not prevent
sharing of IRQ 11.
3. If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other
devices to ensure the proper operation of HPET #3. The PCH hardware does not prevent
sharing of IRQ 12.
4. PIRQ[E:H] are Multiplexed with GPIO pins. Interrupts PIRQ[E:H] will not be exposed if they
are configured as GPIOs.
5.9.3 PCI / PCI Express* Message-Based Interrupts
When external devices through PCI/PCI Express wish to generate an interrupt, they will
send the message defined in the PCI Express* Base Specification, Revision 1.0a for
generating INTA# – INTD#. These will be translated internal assertions/deassertions of
INTA# – INTD#.
5.9.4 IOxAPIC Address Remapping
To support Intel
®
Virtualization Technology, interrupt messages are required to go
through similar address remapping as any other memory request. Address remapping
allows for domain isolation for interrupts, so a device assigned in one domain is not
allowed to generate an interrupt to another domain.
The address remapping is based on the Bus: Device: Function field associated with the
requests. The internal APIC is required to initiate the interrupt message using a unique
Bus: Device: function.
The PCH allows BIOS to program the unique Bus: Device: Function address for the
internal APIC. This address field does not change the APIC functionality and the APIC is
not promoted as a stand-alone PCI device. See Device 31: Function 0 Offset 6Ch for
additional information.
5.9.5 External Interrupt Controller Support
The PCH supports external APICs off of PCI Express ports, and does not support APICs
on the PCI bus. The EOI special cycle is only forwarded to PCI Express ports.
16 PIRQA# PIRQA#
Yes
Internal devices are routable; see
Section 10.1.30 though Section 10.1.45.
17 PIRQB# PIRQB#
18 PIRQC# PIRQC#
19 PIRQD# PIRQD#
20 N/A PIRQE#
4
Yes
Option for SCI, TCO, HPET #0,1,2, 3. Other
internal devices are routable; see
Section 10.1.30 though Section 10.1.45.
21 N/A PIRQF#
4
22 N/A PIRQG#
4
23 N/A PIRQH#
4
Table 5-18. APIC Interrupt Mapping
1
(Sheet 2 of 2)
IRQ #
Using
SERIRQ
Direct
from Pin
Using PCI
Message
Internal Modules
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