Datasheet 167
Functional Description
5.13.6.4 Conditions for Re-Starting the PCI Clock
• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
• When the PCH observes the CLKRUN# signal asserted for 1 (free running) clock,
the PCH deasserts the STP_PCI# signal to the clock synthesizer within 4 (free
running) clocks.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the
PCH again starts driving CLKRUN# asserted.
If an internal source requests the clock to be re-started, the PCH re-asserts CLKRUN#,
and simultaneously deasserts the STP_PCI# signal. For case when PCH distribute PCI
clock, PCH start PCI clocks without the involvement of STP_PCI#.
5.13.6.5 LPC Devices and CLKRUN#
If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA or LPC
serial interrupt, then it can assert CLKRUN#. Note that LPC devices running DMA or bus
master cycles will not need to assert CLKRUN#, since the PCH asserts it on their behalf.
The LDRQ# inputs are ignored by the PCH when the PCI clock is stopped to the LPC
devices in order to avoid misinterpreting the request. The PCH assumes that only one
more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#.
Upon deassertion of STP_PCI#, the PCH assumes that the LPC device receives its first
clock rising edge corresponding to the PCH’s second PCI clock rising edge after the
deassertion.
5.13.7 Sleep States
5.13.7.1 Sleep State Overview
The PCH directly supports different sleep states (S1–S5), which are entered by
methods such as setting the SLP_EN bit or due to a Power Button press. The entry to
the Sleep states is based on several assumptions:
• The G3 state cannot be entered using any software mechanism. The G3 state
indicates a complete loss of power.
5.13.7.2 Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts
to gracefully put the system into the corresponding Sleep state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button
Override event. In this case the transition to the S5 state is less graceful, since
there are no dependencies on DMI messages from the processor or on clocks other
than the RTC clock.
• Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can
occur when system is in S0 or S1 state.
• Shutdown by integrated manageability functions (ASF)
• Internal watchdog timer time-out events
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