Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Functional Description
130 Datasheet
5.4.1.1 LPC Cycle Types
The PCH implements all of the cycle types described in the Low Pin Count Interface
Specification, Revision 1.1. Table 5-7 shows the cycle types supported by the PCH.
NOTES:
1. The PCH provides a single generic memory range (LGMR) for decoding memory cycles and
forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory decode range
is 64 KB in size and can be defined as being anywhere in the 4 GB memory space. This
range needs to be configured by BIOS during POST to provide the necessary memory
resources. BIOS should advertise the LPC Generic Memory Range as Reserved to the OS in
order to avoid resource conflict. For larger transfers, the PCH performs multiple 8-bit
transfers. If the cycle is not claimed by any peripheral, it is subsequently aborted, and the
PCH returns a value of all 1s to the processor. This is done to maintain compatibility with
ISA memory cycles where pull-up resistors would keep the bus high if no device responds.
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
can be to any address. However, the 2-byte transfer must be word-aligned (that is, with an
address where A0=0). A DWord transfer must be DWord-aligned (that is, with an address
where A1 and A0 are both 0).
5.4.1.2 Start Field Definition
NOTE: All other encodings are RESERVED.
Table 5-7. LPC Cycle Types Supported
Cycle Type Comment
Memory Read 1 byte only. (See Note 1 below)
Memory Write 1 byte only. (See Note 1 below)
I/O Read
1 byte only. The PCH breaks up 16- and 32-bit processor cycles into
multiple 8-bit transfers.
I/O Write
1 byte only. The PCH breaks up 16- and 32-bit processor cycles into
multiple 8-bit transfers.
DMA Read Can be 1, or 2 bytes
DMA Write Can be 1, or 2 bytes
Bus Master Read Can be 1, 2, or 4 bytes. (See Note 2 below)
Bus Master Write Can be 1, 2, or 4 bytes. (See Note 2 below)
Table 5-8. Start Field Bit Definitions
Bits[3:0]
Encoding
Definition
0000 Start of cycle for a generic target
0010 Grant for bus master 0
0011 Grant for bus master 1
1111 Stop/Abort: End of a cycle for a target.

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General

Brand	Intel
Model	6 SERIES CHIPSET - DATASHEET 01-2011
Category	Controller
Language	English