Functional Description
118 Datasheet
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5,
F6, F7)
There are eight root ports available in the PCH. The root ports are compliant to the PCI
Express 2.0 specification running at 5.0 GT/s. The ports all reside in Device 28, and
take Function 0 – 7. Port 1 is Function 0, Port 2 is Function 1, Port 3 is Function 2,
Port 4 is Function 3, Port 5 is Function 4, Port 6 is Function 5, Port 7 is Function 6, and
Port 8 is Function 7.
Note: This section assumes the default PCI Express Function Number-to-Root Port mapping is
used. Function numbers for a given root port are assignable through the Root Port
Function Number and Hide for PCI Express Root Ports registers (RCBA+0404h).
PCI Express Root Ports 1–4 or Ports 5–8 can independently be configured as four x1s,
two x2s, one x2 and two x1s, or one x4 port widths. The port configuration is set by
soft straps in the Flash Descriptor.
5.2.1 Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management
events, when enabled. These interrupts can either be pin based, or can be MSIs, when
enabled.
When an interrupt is generated using the legacy pin, the pin is internally routed to the
PCH interrupt controllers. The pin that is driven is based upon the setting of the chipset
configuration registers. Specifically, the chipset configuration registers used are the
D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.
Table 5-5 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
refers to the Hot-Plug and PME interrupt bits.
Table 5-5. MSI versus PCI IRQ Actions
Interrupt Register Wire-Mode Action MSI Action
All bits 0 Wire inactive No action
One or more bits set to 1 Wire active Send message
One or more bits set to 1, new bit gets set to 1 Wire active Send message
One or more bits set to 1, software clears some (but not
all) bits
Wire active Send message
One or more bits set to 1, software clears all bits Wire inactive No action
Software clears one or more bits, and one or more bits
are set on the same clock
Wire active Send message
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