Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Power Plane and States for Output and I;O Signals for Mobile Configurations

Datasheet 101
PCH Pin States
Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 1 of 6)
Signal Name
Power
Plane
During
Reset
1
Immediately
after Reset
1
C-x
states
S0/S1 S3 S4/S5
PCI Express*
PET[8:1]p, PET[8:1]n Core Low Low
4
Defined Defined Off Off
DMI
DMI[3:0]TXP,
DMI[3:0]TXN
Core Low Low Defined Defined Off Off
LPC/FWH Interface
LAD[3:0] / FWH[3:0] Core High High High High Off Off
LFRAME# / FWH[4] Core High High High High Off Off
INIT3_3V#
7
Core High High High High Off Off
SATA Interface
SATA[5:0]TXP,
SATA[5:0]TXN
Core High-Z High-Z Defined Defined Off Off
SATALED# Core High-Z High-Z Defined Defined Off Off
SATAICOMPO Core High-Z High-Z Defined Defined Off Off
SCLOCK/GPIO22 Core
High-Z
(Input)
High-Z (Input) Defined Defined Off Off
SLOAD/GPIO38 Core
High-Z
(Input)
High-Z (Input) Defined Defined Off Off
SDATAOUT[1:0]/
GPIO[48,39]
Core
High-Z
(Input)
High-Z (Input) Defined Defined Off Off
SATA3RBIAS Core
Terminated
to Vss
Terminated to
Vss
Terminate
d to Vss
Terminate
d to Vss
Off Off
SATA3ICOMPO Core High-Z High-Z High-Z High-Z Off Off
SATA3RCOMPO Core High-Z High-Z High-Z High-Z Off Off
Interrupts
PIRQ[A:D]# Core High-Z High-Z Defined Defined Off Off
PIRQ[H:E]# /
GPIO[5:2]
Core
High-Z
(Input)
High-Z (Input) Defined Defined Off Off
SERIRQ Core High-Z High-Z Running High-Z Off Off
USB Interface
USB[13:0][P,N] Suspend Low Low Defined Defined Defined Defined
USBRBIAS Suspend High-Z High-Z Defined Defined Defined Defined