Datasheet 251
Functional Description
Both mechanisms are logically OR’d together such that if any of the mechanisms
indicate that the access should be blocked, then it is blocked. Table 5-58 provides a
summary of the mechanisms.
A blocked command will appear to software to finish, except that the Blocked Access
status bit is set in this case.
5.24.5.2 BIOS Range Write Protection
The PCH provides a method for blocking writes to specific ranges in the SPI flash when
the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type
information (which can be locked down by the initial Boot BIOS) and the address of the
requested command against the base and limit fields of a Write Protected BIOS range.
Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
5.24.5.3 SMI# Based Global Write Protection
The PCH provides a method for blocking writes to the SPI flash when the Write
Protected bit is cleared (that is, protected). This is achieved by checking the Opcode
type information (which can be locked down by the initial Boot BIOS) of the requested
command.
The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as
they do for the FWH BIOS.
5.24.6 Flash Device Configurations
The PCH-based platform must have a SPI flash connected directly to the PCH with a
valid descriptor and Intel Management Engine Firmware. BIOS may be stored in other
locations such as Firmware Hub and SPI flash hooked up directly to an embedded
controller for Mobile platforms. Note this will not avoid the direct SPI flash connected to
PCH requirement.
Table 5-58. Flash Protection Mechanism Summary
Mechanism
Accesses
Blocked
Range
Specific?
Reset-Override
or SMI#-
Override?
Equivalent Function on
FWH
BIOS Range
Write
Protection
Writes Yes Reset Override FWH Sector Protection
Write Protect Writes No SMI# Override
Same as Write Protect in
Intel
®
ICHs for FWH
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