Functional Description
126 Datasheet
5.3.4.1 Wake Up
The integrated GbE controller supports two types of wake-up mechanisms:
1. Advanced Power Management (APM) Wake Up
2. ACPI Power Management Wake Up
Both mechanisms use an internal logic signal to wake the system up. The wake-up
steps are as follows:
1. Host wake event occurs (note that packet is not delivered to host).
2. The 82579 receives a WoL packet/link status change.
3. The 82579 wakes up the integrated GbE controller using an SMBus message.
4. The integrated GbE controller sets the PME_STATUS bit.
5. System wakes from Sx state to S0 state.
6. The host LAN function is transitioned to D0.
7. The host clears the PME_STATUS bit.
5.3.4.1.1 Advanced Power Management Wake Up
Advanced Power Management Wake Up or APM Wake Up was previously known as
Wake on LAN (WoL). It is a feature that has existed in the 10/100 Mb/s NICs for several
generations. The basic premise is to receive a broadcast or unicast packet with an
explicit data pattern and then to assert a signal to wake up the system. In earlier
generations, this was accomplished by using a special signal that ran across a cable to
a defined connector on the motherboard. The NIC would assert the signal for
approximately 50 ms to signal a wake up. The integrated GbE controller uses (if
configured to) an in-band PM_PME message for this.
At power up, the integrated GbE controller reads the APM Enable bits from the NVM PCI
Init Control Word into the APM Enable (APME) bits of the Wake Up Control (WUC)
register. These bits control enabling of APM wake up.
When APM wake up is enabled, the integrated GbE controller checks all incoming
packets for Magic Packets.
Once the integrated GbE controller receives a matching Magic Packet*, it:
• Sets the Magic Packet Received bit in the Wake Up Status (WUS) register.
• Sets the PME_Status bit in the Power Management Control/Status Register
(PMCSR).
APM wake up is supported in all power states and only disabled if a subsequent NVM
read results in the APM Wake Up bit being cleared or the software explicitly writes a 0b
to the APM Wake Up (APM) bit of the WUC register.
Note: APM wake up settings will be restored to NVM default by the PCH when LAN connected
Device (PHY) power is turned off and subsequently restored. Some example host WOL
flows are:
• When system transitions to G3 after WOL is disabled from the BIOS, APM host WOL
would get enabled.
• Anytime power to the LAN Connected Device (PHY) is cycled while in S4/S5 after
WOL is disabled from the BIOS, APM host WOL would get enabled. Anytime power
to the LAN Connected Device (PHY) is cycled while in S3, APM host WOL
configuration is lost.
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