Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - S0 to S5 Timing Diagram

Datasheet 337
Electrical Characteristics
Figure 8-6. S0 to S5 Timing Diagram
Signal NameDestSource
THRMTRIP#CPU PCH
honored
valid
PLTRST#PCH Board
PROCPWRGDPCH Board
PCH
Output Clocks
PCH Board
SLP_S3#PCH Board
PWROKBoard PCH
t218
t219
ignored
t222
SLP_A#
SLP_S4#
SLP_S5#PCH Board
PCH Board
PCH Board
DRAMPWROKPCH CPU
ME-Related Signals
Going to M3: stay high
Going to MOFF: go low
SYS_PWROKBoard PCH
APWROKBoard PCH
t220
t221
May drop before or after
SLP_S4/5# and DRAMPWRGD
CL_RST#PCH
Source of
LANPHYPC value
PCH GbE PHY
Value from MAC
latched in SUS well
Live value from
GbE MAC
Only switch if going to MOFF
If appropriate, save MAC
PMCSR context here
Controller Link
SLP_LAN#PCH Board
SLP_LAN# could stay
high for M3 or WOL
DMI
PCIe Ports
PCH
PCIe*
Devices
normal
operation
L2/L3
DMI Message
L2/L3
SUS_STAT#PCH Board
t214
t215
t217